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VND5050J-E VND5050K-E
Double channel high side driver with analog current sense for automotive applications
Features
General
Max supply voltage Operating voltage range Max On-State resistance (per ch.) Current limitation (typ) Off state supply current
(*) Typical value with all loads connected
VCC VCC RON ILIMH IS
41V 4.5 to 36V 50 m 19 A 2 A(*)

PowerSSO-12
PowerSSO-24
Self limiting of fast thermal transients Protection against loss of ground and loss of VCC Thermal shut down Reverse battery protection (see Figure 28) Electrostatic discharge protection
Application

All types of resistive, inductive and capacitive loads Inrush current active management by power limitation Very low stand-by current 3.0V CMOS compatible input Optimized electromagnetic emission Very low electromagnetic susceptibility In compliance with the 2002/95/ec european directive
Main

Description
The VND5050K-E and VND5050J-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). The device detects open load condition both in on and off state, when STAT_DIS is left open or driven low. Output shorted to VCC is detected in the off state. When STAT_DIS is driven high, STATUS pin is in high impedance state. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears..
Diagnostic Functions

Open drain status output On state open load detection Off state open load detection Thermal shutdown indication
Protections
Undervoltage shut-down Overvoltage clamp Output stuck to VCC detection Load current limitation
Order codes
Package PowerSSO-12 PowerSSO-24 Part number (Tube) VND5050J-E VND5050K-E Part number (Tape & Reel) VND5050J-E13TR VND5050K-E13TR
March 2006
Rev 1
1/28
www.st.com 28
Contents
VND5050J-E / VND5050K-E
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 3.1.2 Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 3.3 3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 C I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 4.2 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 5.2 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
VND5050J-E / VND5050K-E
Block diagram and pin description
1
Figure 1.
Block diagram and pin description
Block Diagram
VCC
GND INPUT1
VCC CLAMP
UNDERVOLTAGE CLAMP 1
STATUS1 STAT_DIS LOGIC INPUT2 STATUS2 OPENLOAD ON 1 OVERTEMP. 1 CURRENT LIMITER 1 DRIVER 1 OUTPUT1
OPENLOAD OFF 1
PWRLIM 1
CONTROL & PROTECTION STATUS2 EQUIVALENT TO CHANNEL1
INPUT2
VCC OUTPUT2
Table 1.
Name VCC
Pin Function
Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Open drain digital diagnostic pin Active high CMOS compatible pin, to disable the STATUS pin
OUTPUTn GND INPUTn STATUSn STAT_DIS
Figure 2.
Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = Vcc GND STAT_DIS INPUT 1 STATUS 1 STATUS 2 INPUT 2 1 2 3 4 5 6 12 11 10 9 8 7 Vcc OUTPUT 1 OUTPUT 1 OUTPUT 2 OUTPUT 2 Vcc
VCC GND. N.C. STAT_DIS INPUT1 STATUS1 N.C. STATUS2 N.C. INPUT2 N.C. VCC OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2
TAB = VCC
PowerSSO-12 Connection / Pin Floating To Ground Status X N.R. N.C. X X Output X N.R.
PowerSSO-24 Input X 10K resistor STAT_DIS X 10K resistor
N.R. = Not recommended
3/28
Electrical specifications
VND5050J-E / VND5050K-E
2
Electrical specifications
Figure 3. Current and Voltage Conventions
IS
VCC
VCC
ISD STAT_DIS VSD IINn INPUTn VINn GND IGND STATUSn OUTPUTn
IOUTn VOUTn ISTATn
VSTATn
VFn = VOUTn - VCCn during reverse battery condition
2.1
Absolute Maximum Ratings
Table 2.
Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Maximum switching energy (L=1.5mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) ) Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - STATUS - STAT_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction Operating Temperature Storage Temperature
Absolute Maximum Ratings
Parameter Value 41 0.3 200 Internally Limited 15 +10 / -1 +10 / -1 +10 / -1 51 Unit V V mA A A mA mA mA mJ
ISTAT_DIS DC Status Disable Current EMAX
VESD
4000 4000 4000 5000 5000 750 -40 to 150 - 55 to 150
V V V V V V C C
VESD Tj Tstg
4/28
VND5050J-E / VND5050K-E
Electrical specifications
2.2
Table 3.
Symbol
Thermal Data
Thermal Data
Value Parameter PowerSSO-12 PowerSSO-24 2.8 See Figure 35 C/W C/W Thermal resistance junction-case (Max.) (with one channel ON) Thermal resistance junction-ambient (Max.) Unit
Rthj-case Rthj-amb
2.8 See Figure 31
2.3
Table 4.
Symbol VCC VUSD VUSDhyst
Electrical Characteristics
8VPower section Parameter Operating supply voltage Undervoltage shutdown Undervoltage shut-down hysteresis On state resistance(2) Clamp Voltage Supply current IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C IS=20mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C VIN=0V; VOUT=4V
(2)
Test Conditions
Min. 4.5
Typ. 13 3.5 0.5
Max. 36 4.5
Unit V V V
RON Vclamp IS
50 100 65 41 46 2(1) 3 0 0 -75 0.01 52 5(1) 6 3 5 0 0.7
m m m V A mA
IL(off1) IL(off2) VF
Off state output current(2) Off state output current(2)
A
Output - VCC diode voltage
-IOUT=4A; Tj=150C
V
(1) PowerMOS leakage included. (2) For each channel
Table 5.
Symbol td(on) td(off)
Switching (VCC=13V)
Parameter Turn-on delay time Turn-off delay time Test Conditions RL=6.5 (see Figure 5) RL=6.5 (see Figure 5) RL=6.5 RL=6.5 Min. Typ. 20 40 see Figure 22 see Figure 24 Max. Unit s s V/s V/s
dVOUT/dt(on) Turn-on voltage slope dVOUT/dt(off) Turn-off voltage slope
5/28
Electrical specifications Table 5.
Symbol WON WOFF
VND5050J-E / VND5050K-E
Switching (VCC=13V) (continued)
Parameter Switching energy losses during twon Switching energy losses during twoff Test Conditions RL=6.5 (see Figure 5) RL=6.5 (see Figure 5) Min. Typ. 0.21 0.28 Max. Unit mJ mJ
Table 6.
Symbol VSTAT ILSTAT CSTAT VSCL
Status Pin (VSD=0V)
Parameter Status Low Output Voltage Status Leakage Current Status Pin Input Capacitance Status Clamp Voltage Protections (1) Parameter DC Short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSDTR) Status Delay in Overload Conditions Turn-off output voltage clamp Output voltage drop limitation Tj>TTSD (see Figure 4) IOUT=2A; VIN=0; L=6mH IOUT=0.1A; Tj= -40C...+150C (see Figure 6) Test Conditions VCC=13V 5VTable 7.
Symbol IlimH IlimL TTSD TR TRS THYST tSDL VDEMAG VON
7 175
TRS + 1 TRS + 5 135
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
6/28
VND5050J-E / VND5050K-E Table 8.
Symbol IOL tDOL(on)
Electrical specifications
Openload Detection
Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Test Conditions VIN = 5V ,8VtPOL
Delay between INPUT falling edge and STATUS rising IOUT = 0A (see Figure 4) edge in Openload condition Openload OFF State Voltage Detection Threshold Output Short Circuit to VCC Detection Delay at Turn Off VIN = 0V, 8V200
500 See Figure 20
1000
s
VOL tDSTKON
2 180
4 tPOL
V s
Table 9.
Symbol VIL IIL VIH IIH VI(hyst) VICL VSDL ISDL VSDH ISDH VSD(hyst) VSDCL
Logic input
Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage STAT_DIS low level voltage Low level STAT_DIS current STAT_DIS high level voltage High level STAT_DIS current VSD = 2.1 V STAT_DIS hysteresis voltage STAT_DIS clamp voltage ISD=1mA ISD=-1mA 0.25 5.5 -0.7 7 VSD = 0.9 V 1 2.1 10 IIN = 1mA IIN = -1mA VIN = 2.1 V 0.25 5.5 7 -0.7 0.9 VIN =0.9 V 1 2.1 10 Test Conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
7/28
Electrical specifications Figure 4. Status Timings
VND5050J-E / VND5050K-E
OPEN LOAD STATUS TIMING (without external pull-up) VIN IOUT < IOL VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up) VIN IOUT < IOL VOUT > VOL
VSTAT tDOL(on) tPOL
VSTAT tDOL(on)
OUTPUT STUCK TO VCC VIN IOUT > IOL VOUT > VOL
OVER TEMP STATUS TIMING Tj > TTSD VIN
VSTAT tDOL(on) tDSTKON
VSTAT tSDL tSDL
Table 10.
Truth table
INPUT L H L H L H L H L H L H OUTPUT L H L X L L L L H H L H SENSE (VCSD=0V)(1) H H H H H L X X L(2) H H (3) L
CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Output Voltage > VOL Output Current < IOL
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. (2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. (3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
8/28
VND5050J-E / VND5050K-E Figure 5. Switching characteristics
VOUT
Electrical specifications
80% dVOUT/dt(on) tr 10%
90% dVOUT/dt(off) tf t
INPUT td(on) td(off)
t
Figure 6.
Output Voltage Drop Limitation
Vcc-Vout
Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
9/28
Electrical specifications Table 11. Electrical Transient Requirements
TEST LEVELS III -75V +37V -100V +75V -6V +40V IV -100V +50V -150V +100V -7V +40V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse
VND5050J-E / VND5050K-E
ISO 7637-2: 2004(E) Test Pulse 1 2a 3a 3b 4 5b(1) ISO 7637-2: 2004(E) Test Pulse 1 2a 3a 3b 4 5b(1) CLASS C E
Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms
Delays and Impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
TEST LEVEL RESULTS III C C C C C C CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. IV C C C C C C
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/28
VND5050J-E / VND5050K-E Figure 7. Waveforms
NORMAL OPERATION INPUT STAT_DIS LOAD CURRENT STATUS UNDERVOLTAGE VCC INPUT STAT_DIS LOAD CURRENT STATUS undefined
VUSDhyst VUSD
Electrical specifications
OPEN LOAD with external pull-up INPUT STAT_DIS LOAD VOLTAGE STATUS OPEN LOAD without external pull-up INPUT STAT_DIS LOAD VOLTAGE LOAD CURRENT STATUS IOUTtPOL
VOL
VOUT>VOL
RESISTIVE SHORT TO Vcc, NORMAL LOAD INPUT STAT_DIS LOAD VOLTAGE STATUS
tDSTKON
IOUT>IOL
VOUT>VOL
VOL
OVERLOAD OPERATION Tj INPUT STAT_DIS LOAD CURRENT STATUS
ILIMH ILIML TR TTSD TRS
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
11/28
Electrical specifications
VND5050J-E / VND5050K-E
2.4
Figure 8.
Iloff1 (uA)
1 0.875 0.75 0.625 0.5 0.375 0.25
Electrical characteristics curves
Off State Output Current Figure 9.
lih (uA)
5 4.5
High Level Input Current
Off state Vcc=13V Vin=Vout=0V
4 3.5 3 2.5 2 1.5 1
Vin=2.1V
0.125 0 -50 -25 0 25 50 75 100 125 150 175
0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 10. Input Clamp Voltage
Vicl (V)
8 7.75
Figure 11. Input High Level
Vih (V)
4 3.5
lin=1mA
7.5 7.25 7 6.75 6.5 6.25 6 -50 -25 0 25 50 75 100 125 150 175 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 12. Input Low Level
Vil (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 13. Input Hysteresis Voltage
Vihyst (V)
2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
12/28
VND5050J-E / VND5050K-E
Electrical specifications
Figure 14. Status Low Output Voltage
Vstat (V)
0.9 0.8
Figure 15. On State Resistance Vs Tcase
Ron (mOhm)
100 90
Istat=1.6mA
0.7 0.6
80 70 60
Iout=2A Vcc=13V
0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175
50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 16. Status Leakage Current
Ilstat (uA)
0.055
Figure 17. On State Resistance Vs VCC
Ron (mOhm)
100 90
0.05
80
Tc= 150C Tc= 125C
Vstat=5V
0.045
70 60
0.04
50 40
Tc= 25C Tc= -40C
0.035
30 20 10
0.03
0.025 -50 -25 0 25 50 75 100 125 150 175
0 0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
Figure 18. Status Clamp Voltage
Vscl (V)
9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175
Figure 19. Openload On State Detection Threshold
Iol (mA)
100 90
Istat=1mA
80 70 60 50 40 30 20 10 0 -50 -25
Vin=5V
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
13/28
Electrical specifications
VND5050J-E / VND5050K-E
Figure 20. Openload Off State Voltage Detection Threshold
Vol (V)
5 4.5
Figure 21. ILIM Vs Tcase
Ilimh (A)
25 22.5
Vin=0V
4 3.5 3 2.5 2 1.5 1 -50 -25 0 25 50 75 100 125 150 175
Vcc=13V
20 17.5 15 12.5 10 7.5 5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 22. Turn-on Voltage Slope
dVout/dt(on) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 23. Undervoltage Shutdown
Vusd (V)
14
Vcc=13V RI=6.5Ohm
12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 24. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
1000 900 800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 25. STAT_DIS Clamp Voltage
Vsdcl(V)
14
Vcc=13V RI=6.5Ohm
12
Isd=1mA
10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
14/28
VND5050J-E / VND5050K-E
Electrical specifications
Figure 26. High Level STAT_DIS Voltage
Vsdh(V)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Figure 27. Low Level STAT_DIS Voltage
Vsdl(V)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
15/28
Application information
VND5050J-E / VND5050K-E
3
Application information
Figure 28. Application schematic
+5V +5V VCC Rprot STAT_DIS
Dld Rprot C OUTPUT Rprot STATUS GND INPUT
VGND
RGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
3.1.1
GND protection network against reverse battery
Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND.
16/28
VND5050J-E / VND5050K-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
C I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k. Recommended values: Rprot =10k, CEXT=10nF.
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL17/28
2.
Application information
VND5050J-E / VND5050K-E
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. Figure 29. Open Load detection in off state
V batt. VCC RPU INPUT DRIVER + LOGIC OUT + STATUS VOL R IL(off2) VPU
RL
GROUND
18/28
VND5050J-E / VND5050K-E
Package and PCB thermal data
4
4.1
Package and PCB thermal data
PowerSSO-12 thermal data
Figure 30. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/W)
70 65 60 55 50 45 40 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
Figure 32. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
Footprint 2 cm2 8 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Pulse Calculation Formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T
19/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 33. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.7 2.8 7 10 22 26 0.001 0.0025 0.05 0.2 0.27 3 0.1 0.8 6 0.1 1 9 10 15 20 9 10 15 2 8
20/28
VND5050J-E / VND5050K-E
Package and PCB thermal data
4.2
PowerSSO-24 thermal data
Figure 34. PowerSSO-24 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 35. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(C/W)
55 50 45 40 35 30 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
Figure 36. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
Footprint 2 cm2 8 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Pulse Calculation Formula Z TH = R TH + Z THtp ( 1 - ) where = tP/T
21/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 37. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2) R1=R7 (C/W) R2=R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7 (W.s/C) C2=C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.4 2 6 7.7 9 28 0.001 0.0022 0.025 0.75 1 2.2 4 5 9 17 9 17 8 10 2 8
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VND5050J-E / VND5050K-E
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 38. PowerSSO-12TM Package Dimensions
D h x 45 C A2 B ddd 12 C 7 A 0.25 mm GAUGE PLANE
SEATING PLANE
C A1 L K
X E H
Y 1 e 6
BOTTOM VIEW
Table 12.
PowerSSO-12TM Mechanical Data
millimeters Min 1.250 0.000 1.100 0.230 0.190 4.800 3.800 5.800 0.250 0.400 0 1.900 3.600 Typ Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000 6.200 0.500 1.270 8 2.500 4.200 0.100
Symbol A A1 A2 B C D E e H h L k X Y ddd
0.800
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Package information Figure 39. PowerSSO-24TM Package Dimensions
VND5050J-E / VND5050K-E
Table 13.
PowerSSO-24TM Mechanical Data
millimeters Min 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.1 0.06 10.1 0.55 4.1 6.5 10.5 0.4 0.85 10deg 4.7 7.1 Typ Max 2.47 2.40 0.075 0.51 0.32 10.50 7.6
Symbol A A2 a1 b c D E e e3 G G1 H h L N X Y
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VND5050J-E / VND5050K-E
Package information
5.2
Packing information
Figure 40. PowerSSO-12 Tube Shipment (No Suffix)
B C
A
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm.
100 2000 532 1.85 6.75 0.6
Figure 41. PowerSSO-12 Tape And Reel Shipment (Suffix "TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Package information Figure 42. PowerSSO-24 Tube Shipment (No Suffix)
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
VND5050J-E / VND5050K-E
C
B
49 1225 532 3.5 13.8 0.6
A
All dimensions are in mm.
Figure 43. PowerSSO-24 Tape And Reel Shipment (Suffix "TR")
REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986
Tape width W Tape Hole Spacing P0 ( 0.1) Component Spacing P Hole Diameter D ( 0.05) Hole Diameter D1 (min) Hole Position F ( 0.1) Compartment Depth K (max) Hole Spacing P1 ( 0.1)
All dimensions are in mm.
24 4 12 1.55 1.5 11.5 2.85 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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VND5050J-E / VND5050K-E
Revision history
6
Revision history
Table 14.
Date 30-Mar-2006
Document revision history
Revision 1 Initial release. Changes
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VND5050J-E / VND5050K-E
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